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CVE-2025-0647

HIGH CVSS: 7.9 Published: 2026-01-14 Modified: 2026-06-17

Description

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

Affected Platforms

Arm Cortex-X3 FirmwareArm Cortex-X3Arm Cortex-X2 FirmwareArm Cortex-X925Arm Cortex-A710Arm C1-UltraArm C1-Ultra FirmwareArm Cortex-X4Arm C1-PremiumArm Neoverse-V2

Weakness Type

CWE-226

References